[NetsPresso] AI Compiler Engineer
👋 About the Team
The NetsPresso Platform Team at Nota AI designs and implements core platforms and software that transform advanced AI model lightweighting and optimization research into real-world products.
Our organization consists of Model Representation, Quantization, Graph Optimization, Model Engineering, and SW Engineering units. Specifically, the Model Representation Part unifies models from various deep learning frameworks into our proprietary NPIR (NetsPresso Intermediate Representation). This foundational step enables the application of optimization technologies such as quantization, graph optimization, and compression.
We secure technical versatility by integrating diverse framework models into NPIR, scale our support for the latest AI models and hardware, and maximize inference efficiency on actual hardware by optimizing the logical structure of deep learning models for target runtime environments.
📌 What You’ll Do at This Position
As a member of this position, you will participate in the productization of the unified IR that serves as the foundation of NetsPresso. You will contribute to designing and developing NPIR by analyzing the characteristics of various deep learning frameworks and hardware.
You will gain hands-on experience applying on-device AI lightweighting and optimization techniques to actual products and solve technical challenges to ensure the latest models run efficiently on diverse hardware. As an AI Compiler Engineer, you will experience the professional fulfillment of implementing theoretical research into a robust software stack.
✅ Key Responsibilities
IR Implementation & Maintenance
- NPIR Graph Structure Development: Implement and extend the data structures for NetsPresso Intermediate Representation (NPIR), designed to represent diverse model architectures from various deep learning frameworks.
- Framework Conversion Logic Development: Develop and validate conversion logic to bridge multiple frameworks (such as PyTorch and ONNX) with NPIR.
Hardware-Friendly IR Transformation & Lowering
- Backend Conversion Logic Development: Implement lowering passes to transform NPIR into target runtimes and hardware-specific IRs (e.g., ExecuTorch, TensorRT).
- Hardware Constraint-Based Graph Transformation: Research and develop hardware optimization techniques based on the analysis of target HW operators and constraints, utilizing compiler and low-level IR analysis technologies.
✅ Requirements
- Degree in Computer Science, Electronic Engineering, or a related field.
- Proficiency in Python with the ability to write Object-Oriented Programming (OOP) and clean code.
- Experience with PyTorch, ONNX, Linux, Git/GitHub, and Docker.
- Minimum of 5 years of relevant professional experience.
- No disqualifications for overseas travel.
✅ Pluses
- Competency in C++ for system-level implementation.
- Basic knowledge of CPU/GPU/NPU memory hierarchy and parallel computing (SIMD, Multi-threading).
- Understanding of compiler fundamentals (e.g., IR, Compiler Pass, AST).
- Experience in model optimization using libraries such as ExecuTorch, ONNX, TensorRT, or AIMET.
- Project experience related to static memory allocation or complex data layout optimization.
✅ Hiring Process
- Document Screening → Pre-assignment Presentation → 1st Interview → 2nd Interview → 3rd Interview
(Additional assignments may be included during the process.)
🤓 A Message from the Team
We value a strong interest in new compiler technologies and hardware backend optimization, along with the execution power to implement these into a sophisticated software stack. This role is not just about theoretical design; it is about productizing the "Lowering" and optimization process so that NPIR achieves peak performance on various hardware backends (NPU, GPU, etc.).
We emphasize a proactive collaborative attitude, communicating closely with other teams based on an understanding of hardware architecture. If you enjoy diving deep into complex operation scheduling and memory optimization to break through the technical limits of On-device AI at the hardware level, you will find great growth opportunities in our team.
Please Check Before Applying! 👀
- This job posting is open continuously, and it may close early upon completion of the hiring process.
- Resumes that include sensitive personal information, such as salary details, may be excluded from the review process.
- Providing false information in the submitted materials may result in the cancellation of the application.
- Please be aware that references will be checked before finalizing the hiring decision.
- Compensation will be discussed separately upon successful completion of the final interview.
- There will be a probationary period after joining, and there will be no discrimination in the treatment during this period.
- To support the employment of persons with disabilities, you may optionally submit a copy of your disability registration certificate under “Additional Documents,” if administrative verification is required. Submission is optional and does not affect the evaluation process.
- Veterans and individuals with disabilities will receive preferential treatment in accordance with relevant regulations.
🔎 Helpful materials
[NetsPresso] AI Compiler Engineer
👋 About the Team
The NetsPresso Platform Team at Nota AI designs and implements core platforms and software that transform advanced AI model lightweighting and optimization research into real-world products.
Our organization consists of Model Representation, Quantization, Graph Optimization, Model Engineering, and SW Engineering units. Specifically, the Model Representation Part unifies models from various deep learning frameworks into our proprietary NPIR (NetsPresso Intermediate Representation). This foundational step enables the application of optimization technologies such as quantization, graph optimization, and compression.
We secure technical versatility by integrating diverse framework models into NPIR, scale our support for the latest AI models and hardware, and maximize inference efficiency on actual hardware by optimizing the logical structure of deep learning models for target runtime environments.
📌 What You’ll Do at This Position
As a member of this position, you will participate in the productization of the unified IR that serves as the foundation of NetsPresso. You will contribute to designing and developing NPIR by analyzing the characteristics of various deep learning frameworks and hardware.
You will gain hands-on experience applying on-device AI lightweighting and optimization techniques to actual products and solve technical challenges to ensure the latest models run efficiently on diverse hardware. As an AI Compiler Engineer, you will experience the professional fulfillment of implementing theoretical research into a robust software stack.
✅ Key Responsibilities
IR Implementation & Maintenance
- NPIR Graph Structure Development: Implement and extend the data structures for NetsPresso Intermediate Representation (NPIR), designed to represent diverse model architectures from various deep learning frameworks.
- Framework Conversion Logic Development: Develop and validate conversion logic to bridge multiple frameworks (such as PyTorch and ONNX) with NPIR.
Hardware-Friendly IR Transformation & Lowering
- Backend Conversion Logic Development: Implement lowering passes to transform NPIR into target runtimes and hardware-specific IRs (e.g., ExecuTorch, TensorRT).
- Hardware Constraint-Based Graph Transformation: Research and develop hardware optimization techniques based on the analysis of target HW operators and constraints, utilizing compiler and low-level IR analysis technologies.
✅ Requirements
- Degree in Computer Science, Electronic Engineering, or a related field.
- Proficiency in Python with the ability to write Object-Oriented Programming (OOP) and clean code.
- Experience with PyTorch, ONNX, Linux, Git/GitHub, and Docker.
- Minimum of 5 years of relevant professional experience.
- No disqualifications for overseas travel.
✅ Pluses
- Competency in C++ for system-level implementation.
- Basic knowledge of CPU/GPU/NPU memory hierarchy and parallel computing (SIMD, Multi-threading).
- Understanding of compiler fundamentals (e.g., IR, Compiler Pass, AST).
- Experience in model optimization using libraries such as ExecuTorch, ONNX, TensorRT, or AIMET.
- Project experience related to static memory allocation or complex data layout optimization.
✅ Hiring Process
- Document Screening → Pre-assignment Presentation → 1st Interview → 2nd Interview → 3rd Interview
(Additional assignments may be included during the process.)
🤓 A Message from the Team
We value a strong interest in new compiler technologies and hardware backend optimization, along with the execution power to implement these into a sophisticated software stack. This role is not just about theoretical design; it is about productizing the "Lowering" and optimization process so that NPIR achieves peak performance on various hardware backends (NPU, GPU, etc.).
We emphasize a proactive collaborative attitude, communicating closely with other teams based on an understanding of hardware architecture. If you enjoy diving deep into complex operation scheduling and memory optimization to break through the technical limits of On-device AI at the hardware level, you will find great growth opportunities in our team.
Please Check Before Applying! 👀
- This job posting is open continuously, and it may close early upon completion of the hiring process.
- Resumes that include sensitive personal information, such as salary details, may be excluded from the review process.
- Providing false information in the submitted materials may result in the cancellation of the application.
- Please be aware that references will be checked before finalizing the hiring decision.
- Compensation will be discussed separately upon successful completion of the final interview.
- There will be a probationary period after joining, and there will be no discrimination in the treatment during this period.
- To support the employment of persons with disabilities, you may optionally submit a copy of your disability registration certificate under “Additional Documents,” if administrative verification is required. Submission is optional and does not affect the evaluation process.
- Veterans and individuals with disabilities will receive preferential treatment in accordance with relevant regulations.